微电子技术论文7581026.pdfVIP

IEEETRANSACTIONSONELECTRONDEVICES,VOL.63,NO.11,NOVEMBER20164233

LateralInAs/Sip-TypeTunnelFETsIntegrated

onSi—Part1:ExperimentalDevices

KirstenEmilieMoselund,SeniorMember,IEEE,DavideCutaia,StudentMember,IEEE,

HeinzSchmid,Member,IEEE,MattiasBorg,Member,IEEE,SaurabhSant,

AndreasSchenk,andHeikeRiel,SeniorMember,IEEE

Abstract—TunnelFETs(TFETs)havebeenidentifiedasthemechanismsandmayachievesubthermalswings.Although

mostpromisingsteepslopedevicesforultralowpowerlogicsubthermalminimumslopeshavebeendemonstrated,experi-

circuits.Inthispaper,wedemonstratein-planeInAs/SiTFETsmentallyobservedslopesaveragedover2–3decadesofcurrent

monolithicallyintegratedonSi,usingourrecentlydeveloped

template-assistedselectiveepitaxyapproach.Thesedevicesrep-areasofyetlargerthan60mV/decade.Thispaperispart1

resentsomeofthemostscaledTFETswithdimensionsoflessofatwo-partpaper,whichsummarizesthecollaborationof

than30nm,combinedwithexcellentaggregateperformancetworesearchgroups.Part1discussesthedevicefabrication

withaveragesubthresholdswing(SS),ofaround70mV/decadeandelectricalcharacterizationofInAs/SiTFETsintegrated

combinedwithIONofafewµA/µmfor|V|=|V|=

DSGSlaterallyonaconventionalsilicon-on-insulator(SOI)sub-

0.5V.Here,wewilldiscussthedevicefabricationaswell

astheexperim