电子科大微电子考研资料数字逻辑7-1.pdfVIP

Chapter7

Sequentiallogicdesign

principles

Therearememorydevicesinthecircuits;

theoutputrelyonbothinputsandstates!

Basicmemorydevices

Latch:theinputsbewatchedcontinuouslyand

outputmaybechangedatanytime

independentoftheclock;

Flip-flop:theinputbesampledandoutputmay

bechangedonlyatthetimesdeterminedbythe

clock!

Bistableelement

Apositivefeedbackcircuitmadebytwo

inverters.

State(Q)canbehold,butcannotbeset!

S-Rlatch

UseNORgatesinsteadinverters:gettwoinputs

whenbothSandRis(00),thestatehold!

WhenSR=(10)Set:setQ=1

WhenSR=(01)Reset:setQ=0

ThetimedelayinS-Rlatch

Initialstate:

Q=0

Laststate:

Q=1

Weneedtimetosetupastablestate!

Ifinputfrom11to00

Initialstate:

Q=0QN=0

Laststate:

Q=?QN=?

Metastable

Theinput(11)shouldbeavoided!

Ifinputsignalistooshort

Initialstate:

Q=0

Laststate:

metastable

S-Rlatch

Wheninputspulseistooshort:metastable!

Minimum-pulse-widthtpw(min):

inputholdtimetoavoidmetastable!

S-Rlatch

UseNANDgates:S−R

WhenS=R=1,bothoutputsare1,but

notcomplementary!

S-Rlatchwithenable

UseANDgatestocontroltheinputs

WhenC=1,itisanormalS-Rlatch;

WhenC=0,bothinputsarecutoff,and

thestateishold!

S-Rlatchwithenable

Theinputpulsemaybecutoffbycontrolsignal!

Holdtime:afterthechangeofC0→1;

Setuptime:beforethechangeofC1→0.

Howtoavoidthemetastable

The