数字设计--第八章.ppt

Chapter8  Sequential Logic Design Practices (时序逻辑设计实践) Contents SSI Latches and Flip-Flops MSI Device: Counters, Shift Registers ( 计数器、移位寄存器) Others: Documentation Standards, Iterative, Failure and Metastability ( 文档标准、迭代、故障和亚稳定性) 8.1 Sequential-Circuit Documentation Standards General Requirements （P680）Logic Symbols ：Rectangular-shaped——inputs on the left, outputs on the right, bubbles for active levels, and so on. Edge-Triggered, Master/Slave Output Asynchronous Preset (at the Top) and Clear (at the Bottom) ( 异步预置（顶端）、异步清零（底端）) 8.1 Sequential-Circuit Documentation Standards State-Machine Description Word descriptions, State tables, State Diagrams, Transition Lists Timing Diagrams and Specifications Most timing diagrams show the relationship between the clock and various input, output, and internal signals. 8.2 Latches and Flip-Flops SSI Latches and Flip-Flops Switch Debouncing ( 开关消抖) Bus Holder Circuit ( 总线保持电路) Bus Holder Circuit ( 总线保持电路) Multibit Registers and Latches Multibit Registers and Latches 4-bit Register 74 x175 8-bit Register 8.4 Counter ( 计数器) The name counter is generally used for any clock sequential circuit whose state diagram contain a Single cycle. Modulus ( 模) : The number of states in the cycle A modulo-m counter, or sometimes, a divide-by-m counter ( 模m 计数器, 又称m 分频计数器）Counter An n-bit binary counter (n 位二进制计数器) ---has n flip-flops and 2n states ---each of theses states is encoded as the corresponding n-bit binary integer. ( 0, 1, 2, …2n-1, 0, 1,…) 计数器的分类按时钟：同步、异步按计数方式：加法、减法、可逆按编码方式：二进制、十进制BCD 码、循环码计数器的功能计数、分频、定时、产生脉冲序列、数字运算本节内容行波计数器、同步计数器MSI 型计数器及其应用二进制计数器状态的译码Ripple Counters （行波计数器）Synchronous Binary Up Counters( 同步二进制加法计数器) Synchronous Counter Synchronous Counters with Enable Input Synchronous Counters with Enable Input Synchronous Binary Up Counters( 同步二进制加法计数器) A 4-Bit Binary Counter 74 x163 A 4-Bit Binary Counter 74 x163 Other MSI Counters 74 x161、74x163 4-Bit Binary Up-Counters (with Asynchronous/Synchronous Clear)