FPGA_层次化设计.pptVIP

Q: how to describe digital system which has several levels? The first method:--Behavioral modeling of 3 input compound gate. entity comb_function is port (a, b, c : in BIT; z: out BIT); end entity comb_function; architecture expression of comb_function is begin z = (not a and b) or (a and c); end architecture expression; -- System top module Programming Architecture aaa of netlist1 is signal p, q, r : BIT; component And2a is port (x, y : in BIT; z: out BIT); end component And2a; Second - Component Instantiation （元件例化） Exercise3: Hierarchical design of a 4-bit adder Ripple adder Exercise4: Hierarchical design of counters circuit of #100 counter CNT10.VHD Waveform analyze of #100 counter * Top Module Sub Module A Sub Module B Sub Module C Module A1 Module A2 Module B1 Module B2 Module C1 Module C2 Module C3 Top entity setting Hierarchical Design —— Design Level We can deduce Another method: structural modeling p q r entity And2A is port (x, y : in BIT; z: out BIT); end entity And2A; architecture ex1 of And2A is begin z = x and y; end architecture ex1; entity Or2B is port (x, y : in BIT; z: out BIT); end entity Or2B; architecture ex1 of Or2B is begin z = x or y; end architecture ex1; entity Not1A is port (x : in BIT; z: out BIT); end entity Not1A; architecture ex1 of Not1A is begin z = not x; end architecture ex1; Sub modules programming g2 g3 g4 g1 netlists Library ieee; Use ieee.std_logic_1164.all; entity netlist1 is port (a, b, c : in BIT; z: out BIT); end entity netlist1 ; component Or2b is port (x, y : in BIT; z: out BIT); end component Or2b; component Not1a is port (x : in BIT; z: out BIT); end component Not1a; begin g1: Not1a port map (x=a, z=p); g2: And2a port map (x= p, y= b, z= q); g3: And2a port map (x= a, y= c, z= r); g4: Or2b port map (x= q, y= r, z= z); end architecture aaa; Component元件实体名 port 元件端口信息，与该元件实现时