EDA技术与应用_有限状态机设计.pptVIP

有限状态机设计;教学重点;8.1 有限状态机;摩尔型（Moore）状态机 ;Moore型状态图;Mealy型状态图;【例10.7】状态机设计举例 module FSM( clk, clr, out, start, step2, step3 ); input clk, clr, start, step2, step3; output[2:0] out; reg[2:0] out; reg[1:0] state, next_state; parameter state0 = 2’b00, state1 = 2’b01, // 状态编码 state2 = 2’b11, state3 = 2’b10; // 格雷码 always @( posedge clk or posedge clr ) begin if( clr ) state = state0; // 定义初态 else state = next_state; end;always @( state or start or step2 or step3 ) // 状态转换 begin case (state) state0: begin if( start ) next_state = state1; else next_s