基于Verilog的FPGA与USB 2.0接口电路的设计研究.docVIP

基于Verilog的FPGA与USB 2.0接口电路的设计研究 申 请 人: 周艳鑫 学 号: 培养单位: 学科专业: 研究方向: 指导教师: 邱成军教授 完成日期: 年月日 中文摘要 串行总线USB 2.0采集数据高速传输通用规范；被国际著名计算机厂家广泛采用，是目前计算机与外数据接口的流行配置。掌握USB 2.0采集、传输协议和工作机制，可以更好地实现计算机之间的数据通讯，提高数据通讯的准确性和工作效率。本课题研究的USB 2.0接口芯片为FX2 CY7C68013，其工作模式为Slave FIFO，本文采用了FPGA为其核心控制系统，更好地扩展该芯片使用功能，对其内部的FIFO进行控制，实现数据的高速传输。该系统主要由USB驱动程序和FPGA控制软件模块组成，通过Verilog HDL硬件描述语言实现FPGA与接口芯片控制器的控制。USB 2.0接口芯片FX2 CY7C68013）设定在Slave FIFO从机工作模式，在FPGA中用Verilog HDL产生应的写、读信号，经过计算机仿真实现数据的快速读写操作。仿真实验结果验证了FPGA驱动USB 2.0接口芯片FX2 CY7C68013）方法的可行性，该系统的数据通讯具有传输准确、速度快等特点，高速数据传输或采集系统中。 关键词：Slave FIFO 模式； FPGA ；USB 2.0接口 Abstract Serial Bus USB 2.0 is a general specification of high-speed data acquisition and transmission.Widely used by internationally well-known computer manufacturers,it is the popular configuration of computer and external data interface currently.Mastering USB 2.0 collection,transport protocol and working mechanism can better realize the data communication among computers and improve the accuracy and efficiency of data communication.The USB 2.0 interface chip of this research is FX2 CY7C68013,its operating mode is Slave FIFO.In order to better expand the chip function,this paper adopts FPGA as the core control system, using FPGA for its internal control of FIFO to achieve high-speed data transmission. This system module is mainly composed of the USB driver and the FPGA control software.Through the Verilog HDL hardware description language to achieve the control of the interface chip controller and FPGA.CY7C68013 is set in the slave mode of the Slave FIFO,using Verilog HDL to produce corresponding reading, writing control signal in the FPGA.Through computer simulation realizes data fast reading and writing operations.The simulation results verify the feasibility of FPGA driver USB 2.0 interface chip FX2 CY7C68013.The system data communication provides the transmission accuracy, speed and other characteristics,which can be applied to the USB 2 i