Lecture 10MPC 555 Interrupt.ppt

Week 9 ISU, CprE 211, Sp04 Lecture 10MPC 555 Interrupt Interrupt System Design: Hardware issues Connect interrupt sources to processor core. Determine ISR addresses using exception vector table. Help software determine interrupt source. Disable/enable interrupts. Mask interrupts. Interrupt System Design: Software Issues Interrupt setup Set up interrupt level Set up exception vector table Set up interrupt mask Enable interrupt Device-specific setup Interrupt Processing Create/destroy stack frame Save/restore machine states and EPC Mask interrupt (optional) Enable interrupt (optional) Save/restore registers contents Determine interrupt source Determine ISR address Device-specific processing MPC555 Interrupt Overview MPC555 Interrupt Sources: External I/O devices Internal I/O device From USIU inside (Unified System Interface unit) USIU includes interrupt control PowerPC Internal I/O Modules TPU3: Time Processor Units, 3rd version; versatile functions, e.g. counting pulses MIOS1: Modular I/O System; QADC64: Queued Analog-to-digital converter TouCAN: Control Area Network, two-wire, up to 1Mbps and 40m; e.g. network inside vehicle QSMCM: Queued Serial Multi-channel Module IMB3 bus: Inter-Module Bus UIMB: U-bus to IMB Interface UIMB: U-bus to IMB interface UIPEND: Interrupt pending reg. U-bus: Unified bus, connecting multiple internal buses UMCR[IRQUX]: Enable level 7-31 UIMB: U-bus to IMB Interface The interface converts 32 interrupt levels on IMB3 Bus to 8 interrupt levels on U-Bus Level 0-6 to U-Bus level 0-6 Level 7-31 to U-Bus level 7 Interrupt handler reads full UIPEND through memory-mapped I/O External Interrupts Other I/O device: Hard drive, video card, … IRQ[0]: connect to reset Unified System Interface Unit The USIU controls system start-up, system initialization and operation, system protection, and the external system bus. MPC555 USIU functions: System configuration and protection Interrupt controller System reset monitoring and generation Clock syn