Berkeley EE142 project.pdfVIP

University of California, Berkeley Fall 2005 EECS 142 Prof. A. Niknejad A Direct Conversion Receiver Project Due December 9, 2005 VGA ADC I LNA VGA ADC Q An integrated CMOS direct conversion receiver is shown above. This radio operates in the 2.4 GHz band with 1 MHz channel bandwidth. Design the front-end LNA and I/Q mixers in the 65 nm CMOS technology using the BSIM4 Berkeley Technology Model. The specifications for the design are summarized below: • Power gain of 40 dB or more to baseband. The signal bandwidth is 1 MHz. Maintain 1 dB of gain flatness. • System noise figure of 5 dB. Integrate the noise figure from 1 kHz − 1 MHz. • Input and output match better than 20 dB. Zin = 50Ω and Zout = 300Ω. • A third-order linearity better than IIP3 −20 dBm. Second order linearity IIP2 +10 dBm. For the IIP3 test assume two tones at 50 MHz and 100 MHz offset. For IIP2 use two tones at 150 MHz and 200 MHz offsets. • LO leakage at the LNA input: −100 dBm max. • Image rejection 30 dB. Discuss your assumptions in acheiving this level of rejection. Assume that a bandgap referenced current source is available for biasing. You should generate all bias voltages and currents from this bandgap. Carefully consider the layout of the MOSFET and specify the transistor parasitic area parameters in SPICE/Spectre (Diffusion area, Adiff = 0.5 µm × W ; diffusion periphery = W . For a cascode you should share junctions to reduce the diffusion area). You may employ inductors with a QL = 6 for L 10 nH), and QL = 3 for L 20 nH. The capacitors have a QC = 20