Lecture 13 Cache and Virtual Memroy Review.ppt

Lecture 13: Cache and Virtual Memroy Review Cache optimization approaches, cache miss classification, What Is Memory Hierarchy A typical memory hierarchy today: Here we focus on L1/L2/L3 caches and main memory Why Memory Hierarchy? 1980: no cache in μproc; 1995 2-level cache on chip(1989 first Intel μproc with a cache on chip) Generations of Microprocessors Time of a full cache miss in instructions executed: 1st Alpha: 340 ns/5.0 ns = ?68 clks x 2 or 136 2nd Alpha: 266 ns/3.3 ns = ?80 clks x 4 or 320 3rd Alpha: 180 ns/1.7 ns =108 clks x 6 or 648 1/2X latency x 3X clock rate x 3X Instr/clock ? 4.5X Area Costs of Caches Processor % Area %Transistors (-cost) (-power) Intel 80386 0% 0% Alpha 21164 37% 77% StrongArm SA110 61% 94% Pentium Pro 64% 88% 2 dies per package: Proc/I$/D$ + L2$ Itanium 92% Caches store redundant dataonly to close performance gap What Is Cache, Exactly? Small, fast storage used to improve average access time to slow memory; usually made by SRAM Exploits locality: spatial and temporal In computer architecture, almost everything is a cache! Register file is the fastest place to cache variables First-level cache a cache on second-level cache Second-level cache a cache on memory Memory a cache on disk (virtual memory) TLB a cache on page table Branch-prediction a cache on prediction information? Branch-target buffer can be implemented as cache Beyond architecture: file cache, browser cache, proxy cache Here we focus on L1 and L2 caches (L3 optional) as buffers to main memory Example: 1 KB Direct Mapped Cache Assume a cache of 2N bytes, 2K blocks, block size of 2M bytes; N = M+K (#block times block size) (32 - N)-bit cache tag, K-bit cache index, and M-bit cache The cache stores tag, data, and valid bit for each block Cache index is used to select a block in SRAM (Recall BHT, BTB) Block tag is compared with the input tag A word in the data block may be selected as the output For Questions About Cache Design Blo