CS 161Computer Architecture Chapter 5Lecture 9.ppt

CS 161Computer Architecture Chapter 5Lecture 9 Instructor: L.N. Bhuyan /~bhuyan Adapted from notes by Dave Patterson(/~patterson) Where We Are: Machine Organization MIPS-lite processor Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”) just enough to illustrate key ideas instruction set subset (3 groups): arithmetic-logical: add, sub,  and, or,  slt memory reference: lw, sw control flow: j, beq can we write real programs with just these? Need up to 5 steps to execute any instruction in our subset: Step 1: fetch instruction Step 2-5: ? Instruction Execution Steps 1. Read IM[PC] 2. Instruction Decode, PC = PC + 4, Register read ALU operation, Branch address computation LW/STORE in Data memory Register Write building a Datapath for MIPS (step 1) Datapath Step 1: any instruction building a Datapath for MIPS (step 2) Datapath Step 2: any instruction Up to 5 Steps in Executing MIPS Subset 3rd step onwards depends on instruction class EX: for ALU instructions, add $t0, $t1, $t2 outputs from registers t1 and t2 will be sent to the ALU input. For Memory-reference instruction: Address ? Base + offset lw $t0,20($s0) building a Datapath for MIPS (lw step 3) Datapath Step 3-4: R-format Instructions Datapath Step 3: Branch Datapath Step 3: Branch Up to 5 Steps in Executing MIPS Subset 4th step depends on instruction class Ex: for lw: Fetch Data from MemoryData ? Mem[Address] For sw: Put the contents of a register in Memory Datapath Step 3-5: Load/Store Compose Datapath: R-form + Load/Store .* 1999 ?UCB Personal Computer Processor (CPU) Computer Control (“brain”) Datapath (“brawn”) Memory Devices Input Output Arithmetic-Logic Unit(ALU) Chap. 7 (done) Chap. 8 Processor = Chaps. 5 NOW Chap 5 : 2 weeks Chap 6 : 1 week Chap 7 : 3 weeks Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory operation Write Back PC Memory Step 1 . . . add $t0,$t0,$t0 add $t0,$s1,$t0 lw $t1,20($s0)