Chapter 3 Combination and Sequential Circuits Modeling.ppt

Chapter 3 : Combination and Sequential Circuits Modeling SC_MODULE SC_MODULE (module_name) { // declarations of ports : input, output and inout // Declarations of signals used in inter-process // Communication // Process method declarations // Other (non-process) methods // Child module instantiation pointer declarations // Data variable declarations SC_CTOR (module_name) { //Child module instantiations and interconnections SC_METHOD (process_method_name); // Sensitivity list for process SC_THREAD (process_method_name); // Sensitivity list for process Combination Logic : Single Process SC_MODULE (mac) { sc_inint a, b, c; sc_outint sum; void proc_mac() { sum = a * b + c;}; SC_CTOR(mac) { SC_METHOD(proc_mac) sensitive a b c; } }; Combination Logic Multiple Processes SC_MODULE (mult_procs) { Sc_intbool source; Sc_outbool drain; Sc_signalbool connect1, connect2; void mult_procs_1() { connect1 = !source;); void mult_procs_2() { connect2 = !connect;}; void mult_procs_3() { drain = !connect2;}; SC_CTOR (mult_procs) { SC_METHOD (mult_procs_1); sensitvie source; SC_METHOD (mult_procs_2); sensitvie connect1; SC_METHOD (mult_procs_3); sensitvie connect2; } }; Sequential Logic Example SC_MODULE (count4) { //sc_in_clk ? sc_inbool sc_in_clk clk; sc_inbool rst; sc_outint cout; int curValue; void proc_mac() { curValue = rst ? 0 : curValue + 1; cout = curValue;}; SC_CTOR(mac) { SC_METHOD(proc_mac) sensitive_pos clk rst; //async reset sensitive_pos clk; //sync reset } }; Port Read and Write Issues Code SC_MODULE (xor) { sc_insc_uint4 bre, sty; sc_outsc_uint4 tap; void proc_xor() { tap = bre ^ sty;}; SC_CTOR (xor) { SC_METHOD (proc_xor); sensitive bre sty; } }; Compiler error error C2678: 二元運算子 ^ : 找不到使用左方運算元型別 sc_inT 的運算子 (或是沒有可接受的轉換) with [ T=sc_dt::sc_uint4 ] Port Read and Write Issues (cont.) Code SC_MODULE (xor) { sc_insc_uint4 bre, st