[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 5 behavioral.ppt

[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 5 behavioral.ppt

Behavioral Design Style: Registers, Counters, Shift Registers Required reading Optional Reading What is a PROCESS? A process is a sequence of instructions referred to as sequential statements. Anatomy of a Process Statement Part Contains Sequential Statements to be Executed Each Time the Process Is Activated Analogous to Conventional Programming Languages PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT

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