[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 9 ASM.pptVIP

Required reading Algorithmic State Machine Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables. Elements used in ASM charts (1) Elements used in ASM charts (2) State box – represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be u