[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 6 mixed.pptVIP

Mixing Design StylesSynthesis Modeling of circuits with regularstructure VHDL Design Styles Mixed Style Modeling architecture ARCHITECTURE_NAME of ENTITY_NAME is Here you can declare signals, constants, functions, procedures… Component declarations No variable declarations !! begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Process statement inside process you can use only sequential statements end ARCHITECTURE_NAME; PRNG Example (1)