[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 8 state machines.ppt

Finite State Machines Required reading Optional Reading Structure of a Typical Digital System Execution Unit (Datapath) Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task Examples of Resources Adders, Multipliers, Registers, Memories, etc. Control Unit (Control) Controls Data Movements in the Execution Unit by Switching Multiplexers and Enabling or Disabling Resources Follows Some ‘Program’ or Schedule Often Implemented as Finite State Machine or collection of Finite State Machines Finite State Machines (FSMs) Any Circuit with Memory Is a Finite State M