串行解串器的四种不同架构.pdfVIP

DesignCon 2004 SerDes Architectures and Applications Dave Lewis, National Semiconductor Corporation Abstract When most system designers look at serializer/deserializer (SerDes) devices, they often compare speed and power without considering how the SerDes works and what it actually does with their data. Internal SerDes architecture may seem irrelevant, but this overlooked item can dictate many important system parameters like system topology, protocol overhead, data formatting and flow, latency, clocking and timing requirements, and the need for additional buffering as well as logic. These issues can have a big impact on system cost, performance, and efficiency. There are at least four distinct SerDes architectures. They include: parallel clock SerDes, 8b/10 SerDes, embedded clock bits (alias start-stop bit) SerDes, and bit interleaving SerDes. Each one has evolved over the years to address a certain set of system design issues. This paper unveils the inner workings of these four SerDes architectures, examines their differences, and shows how each fits an important range of today’s applications. Author(s) Biography Dave Lewis is a Technical Marketing Manager in National Semiconductors PC Networking Group, handling high-speed interface products. He is the author of many articles and design guides including the original LVDS Owners Manual. He holds a BSEE from the University of California at San Diego. Introduction Serial interconnects form the critical backbone of modern communications systems, so the choice of serializer/deserializer (SerDes) can have a big impact on system cost and performance. While the maze of choices may seem confusing at first, SerDes devices fall into a few basic architectures, each tailored to specific application requirements. A basic understanding of these architectural differences enables the designer to quickly find the right SerDes for the application. In this article we examine four distinct SerDes archit