BDDbased Verification of Scalable Designs.pdfVIP

ˇ FACTA UNIVERSITATIS (NI S) SER .: ELEC . ENERG . vol. 20, no. 3, December 2007, 367-379 BDD-based Verification of Scalable Designs Daniel Große and Rolf Drechsler Abstract: Many formal verification techniques make use of Binary Decision Dia- grams (BDDs). In most applications the choice of the variable ordering is crucial for the performance of the verification algorithm. Usually BDDs operate on the Boolean level, i.e. BDDs are a bit-level data structure. In this paper we present a method to speed-up BDD-based verification of scalable designs that makes use of a learning pro- cess for word-level information. In a pre-processing a scalable ordering is extracted from the RTL that is used as a static ordering for large designs. Experimental results show that significant improvements can be achieved. Keywords: BDD, Variable ordering, Verification, RTL, Word-level Information 1 Introduction As modern circuits contain up to several million transistors, verification has be- come the major bottleneck in the design flow, i.e. up to 80% of the overall design costs are due to verification. This is one of the reasons why recently several formal verification methods have been developed since classical simulation cannot guar- antee sufficient coverage of the design. For example, in [1] it has been reported that for the verification of the Pentium IV more than 200 billion cycles have been sim- ulated, but this only corresponds to 2 CPU minutes, if the chip is run at 1 GHz. As alternatives, formal verification or symbolic simulation have been proposed and in the meantime these have been successfully applied in many projects [2, 3]. In this context many alternative techniques have been proposed that are used to speed up the proof process, such as Boolean Satisfiability (SAT) [4, 5, 6] or Binary Decision Diagrams