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Chapter 14
Nano-Underfills for Fine-Pitch Electronics
Pradeep Lall(*ü ), Saiful Islam, Guoyun Tian, Jeff Suhling, and Darshan Shinde
14.1 Introduction
Packaging materials undergo dimensional changes under environmental exposure to
temperature change. Thermomechanical cyclic loads induce stresses and damage
interconnects. Underfills compensate for the mismatch in coefficient of thermal expan-
sion (CTE) between silicon and the printed circuit board (PCB), and have been used
as a supplemental restraint mechanism to enhance the reliability for flip-chip devices
and chip-scale packages in a wide variety of applications including portable consumer
electronics such as cellular phones, laptops, under-the-hood electronics, microwave
applications, system in package (SIP), high-end workstations, and several other
high-performance applications. Figure 14.1 shows an underfilled flip-chip assembly,
with solder interconnects between the silicon chip and the PCB. It surrounds the solder
balls. Underfill technology has evolved to meet the demand of decreasing feature size
and increasing input/output (I/O) number in the integrated circuit (IC) chip.
14.2 Potential of Nano-Underfills
Capillary-flow underfills rely on the flow of the underfill into the gap between the
bonded die and substrate. This process may be slow and often requires a batch cure
after dispense. No-flow underfills are an attractive alternative to the use of
capillary-flow underfills, and eliminate the need for postreflow batch cure opera-
tion and reduce production cycle time. Instead, no-flow underfills are cured during
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