Lesson 13 Overview of modern digital system design.pptVIP

Lesson 13 Overview of modern digital system design.ppt

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Lesson 13 Overview of modern digital system design.ppt

本文观看结束!!! Design automation Digital design has become very dependent on CAD – also known as DA or EDA The EDA tools allow two tasks to be performed Synthesis Simulation Methods for digital design description schematic capture hardware description language (HDL) Verilog VHDL Logic gates The basic building blocks of digital circuits A gate is an electronic component with a number of inputs and, generally, a single output. The inputs and the outputs are normally in one of two states: logic 0 or logic 1. These logic values are represented by voltages (for instance, 0 V for logic 0 and 3.3 V for logic 1) or currents. The gate itself performs a logical operation using all of its inputs to generate the output. It is possible to buy a single integrated circuit containing, say, four identical gates, as shown in Figure 5.1. (Note that two of the connections are for the positive and negative power supplies to the device. These connections are not normally shown in logic diagrams.) A digital system could be built by connecting hundreds of such devices together - indeed many systems have been designed in that way. Figure 5.1 A small-scale integrated circuit Logic gates ASICs and FPGAs Full-custom and semi-custom ICs ASICs Programmable logic devices PLAs (programmable logic arrays ) PALs (programmable array logic) CPLDs (complex PLDs) FPGAs (field programmable gate arrays). Figure 5.2 PLA structure. ASICs and FPGAs Design flow Write a specification. If necessary, partition the design into smaller parts and write a specification for each part. From the specification draw a state machine chart. This shows each state of the system and the input conditions that cause a change of state, together with the outputs in each state. Minimize the number of states. This is optional and may not be useful in all cases. Design flow Assign Boolean variables to represent each state. Derive next state and output logic. Optimize the next state and output logic to minimize the number of

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