《EDA作业答案》.docVIP

作业 讲解P92:3-2、3-3、3-4(1)、3-5、3-12、3-14 P92:3-2 Library ieee; Use ieee.std-logic-1164.all; Entity mux41 is Port(s0,s1,a,b,c,d: in std-logic; y: out std-logic); end mux41; architecture one of mux41 is begin process(s0,s1,a,b,c,d) begin if s0=‘0’and s1=‘0’then y﹤=a; elsif s0=‘1’and s1=‘0’then y﹤=b; elsif s0=‘0’and s1=‘1’then y﹤=c; else y﹤=d; end if; end process; end one; Library ieee; Use ieee.std-logic-1164.all; Entity mux41 is Port(s0,s1,a,b,c,d: in std-logic; y: out std-logic); end mux41; architecture one of mux41 is signal stmp: std-logic-vector(1 downto 0); begin stmp﹤=s1s0; process(s0,s1,a,b