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《EDA作业答案》.doc
作业
讲解P92:3-2、3-3、3-4(1)、3-5、3-12、3-14
P92:3-2
Library ieee;
Use ieee.std-logic-1164.all;
Entity mux41 is
Port(s0,s1,a,b,c,d: in std-logic;
y: out std-logic);
end mux41;
architecture one of mux41 is
begin
process(s0,s1,a,b,c,d)
begin
if s0=‘0’and s1=‘0’then y﹤=a;
elsif s0=‘1’and s1=‘0’then y﹤=b;
elsif s0=‘0’and s1=‘1’then y﹤=c;
else y﹤=d;
end if;
end process;
end one;
Library ieee;
Use ieee.std-logic-1164.all;
Entity mux41 is
Port(s0,s1,a,b,c,d: in std-logic;
y: out std-logic);
end mux41;
architecture one of mux41 is
signal stmp: std-logic-vector(1 downto 0);
begin
stmp﹤=s1s0;
process(s0,s1,a,b,c,d)
begin
case stmp is
when“00”=﹥y﹤=a;
when“01”=﹥y﹤=b;
when“10”=﹥y﹤=c;
when“11”=﹥y﹤=d;
when others=﹥null;
end case;
end process;
end one;
P92:3-3
Entity muxk is
Port(s0,s1,a1,a2,a3: in bit;
outy: out bit);
end muxk;
architecture one of muxk is
signal tmp :bit;
begin
process(s0,a2,a3)
begin
case s0 is
when‘0’=﹥tmp﹤=a2;
when‘1’=﹥tmp﹤=a3;
when others=﹥null;
end case;
end process;
process(s1,tmp,a1)
begin
case s1 is
when‘0’=﹥outy﹤=a1;
when‘1’=﹥outy﹤=tmp;
when others=﹥null;
end case;
end process;
end one;
P92:3-4(1)
x1 0 0 1 1
y1 0 1 0 1
diff 0 1 1 0
s-out 0 1 0 0
Library ieee;
Use ieee.std-logic-1164.all;
Entity h-suber is
Port(x1, y1: in std-logic;
diff, s-out : out std-logic);
end h-suber;
architecture one of h-suber is
begin
diff﹤=x1 xor y1;
s-out﹤=(not x1) and y1;
end one;
Library ieee;
Use ieee.std-logic-1164.all;
Entity or2a is
Port(a, b: in std-logic;
c : out std-logic);
end or2a;
architecture two of or2a is
begin
c﹤=a or b;
end two;
Library ieee;
Use ieee.std-logic-1164.all;
Entity f-suber is
Port(x, y, sub-in: in std-logic;
diffr, sub-out : out std-logic);
end f-suber;
architecture three of f-suber is
component h-suber
port(x1,y1: in std-logic;
diff, s-out: out std-logic);
end component;
component or2a
port(a, b: in std-logic;
c: out std-logic);
end component;
signal t0, t1, t2: std-logic;
begin
u1: h-suber port map(x1=﹥x, y1
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