《帧同步检测电路代码》.docVIP

// FSM: one hot with zero-idle encoding `timescale 100 ps / 1 ps module synDetect(clk,rst,din,synFlag); input clk; // clock input rst; // reset signal 1(high) is availiable input din; // the detect signal output synFlag; // synchronization indication parameter N1 = 3, N2 = 5, NBITS = 3; parameter [3:1] //ERROR // one hot with zero-idle for state LOST = 3d1, PRE_SYN = 3d2, SYN = 3d3; reg [3:1] nxState; // the next state reg [3:1] pState; // the present state reg [NBITS-1:0] cntN1; // the counter for N1 reg [NBITS-1