EffectofHighPressureDeuteriumAnnealingon-Sematech.PDF

Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate H. Park, M. Chang, H. Yang, M. S. Rahman, M. Cho, B.H. Lee*, R. Choi*, and H. Hwang 2004. 12. 3. 2004. 12. 3. Gwangju Institute of Science and Technology, KOREA, *SEMATECH Outline A. Effects of high pressure annealing on Hf-based gate dielectrics A. Effects of high pressure annealing on Hf-based gate dielectrics Improvement of device performance Effect of deuterium concentration Device reliability with subsequent N2 annealing Effect of fluorine annealing B. Effects of high Pressure H annealing on SOI MOSFETs B. Effects of high Pressure H2 annealing on SOI MOSFETs 2 Improvement of bottom Si/SiO2 interface quality C. Effects of high Pressure annealing on Metal gate MOSFET C. Effects of high Pressure annealing on Metal gate MOSFET Metal electrode dependent interface trap generation Mobility improvement with high pressure annealing Gwangju Institute of Science and Technology, KOREA Gwangju Institute of Science and Technology, KOREA Motivations High interface trap density at high-k/Si significantly degrades MOSFET mobility To completely passivate interface traps, *References o o high temperature FG PDA (450 C~600 C) K. Onishi et al. is introduced recently* “Effects of high-temperature forming gas anneal on HfO2 MOSFET