SynthesisforCMOSPTLLogic-Universityof.pptVIP

March 2000 DATE-2000 CMOS/PTL Motivation Traditional logic synthesis (SIS) use factored forms, algebraic factorization: a(b+c) boolean formulas treated as polynomials: F = ac + bc + ad + bd = (a + b) (c + d) weak Boolean factorization capability F = a + bc = (a + b)(a + c) …. cannot be found easily good for AND/OR, difficult to identify XOR and MUX logic Our approach based on BDD representation of logic truly Boolean operations, Boolean algebra rules applied: a + a = a, a * a’ =0, a * 1 = a, a * 0 = 0, etc can easily identify XOR, MUX structures very fast BDD-based Logic Decomposition Simple dominators Algebraic AND, OR, XOR decomposition Generalized dominators Boolean AND, OR, XOR decomposition Cofactor, single/super node Simple/complex MUX XOR Decomposition – Role of X-dominator Decomposition of Multiple-output Functions Build BDD for each output Decompose each BDD Construct factoring trees Identify logic sharing Application to CMOS/PTL Logic Synthesis Logic balancing Reduction of long transistor chains Fanout reduction Application to CMOS/PTL Logic Synthesis Preliminary Results – XOR Intensive Logic Comparison with SIS and [tsai’96] # XOR’s: after/before technology mapping SIS mapper used (lower cost assigned to XOR gates) March 2000 DATE-2000 CMOS/PTL * March 2000 DATE-2000 CMOS/PTL *DATE-2000 March 2000 DATE-2000 CMOS/PTL Synthesis For CMOS/PTL Circuits Congguang Yang Maciej Ciesielski Dept. of Electrical Computer Engineering University of Massachusetts, Amherst Sponsored by NSF Observation: BDD structure reveals functional decomposition. Identify Dominators (BDD structures) ? different logic decompositions 0 1 D = a + b b a 0 1 F = a + bc c a b 0 1 Q = a + c c a F = a + bc = (a + b)(a + c) = * Boolean AND/OR decomposition Boolean AND decomposition - example g d e a f b b c c Q 1 DC 0 DC minimize g d e a Q 1 0 Q = ag + d + e a f b b c c 0 0 D 1 reduce D = af + b + c a f b c 0 D 1 g d e a f b b c c F 1 0 0 F = D Q