CMOS制造工艺及流程——Good.pptVIP

* Part 2: Open discussion Mask tooling(0.35um 1P4M logic process ); Design rule (0.35um 1P4M logic process). * Mask tooling 0.35um Logic Process Mask Tooling Information * Brief Design Rule-FEOL * Brief Design Rule-BEOL * 0.35um 1P4M logic process design rule check 0.35um 1P4M logic process design rule Design rule check data * Device Performance- HNMOS window: poly CD:0.45-0.6um * Device Performance- HPMOS window- poly CD:0.45-0.65um * Device Performance-LNMOS window- poly CD:0.32-0.4um * Device Performance- LPMOS window- poly CD:0.32-0.4um * Thanks!! * P-衬底 N+ N+ POLY栅 N- N- 图三：轻掺杂漏结构 N+ N