a scalable thread scheduling co-processor based on data-flow principles：一种基于数据流原理的可伸缩线程调度协处理器.pdfVIP

Future Generation Computer Systems 53 (2015) 100–108 Contents lists available at ScienceDirect Future Generation Computer Systems journal homepage: /locate/fgcs A scalable thread scheduling co-processor based on data-flow principles R. Giorgi ∗, A. Scionti University of Siena, Department of Information Engineering and Mathematics, Via Roma 56, Siena, Italy h i g h l i g h t s • We present a data-flow based co-processor supporting the execution of fine-grain threads. • We propose a minimalistic core ISA extension for data-flow threads. • We propose a two-level hierarchical scheduling co-processor that implements the ISA extension. • We show the scalability of the proposed system through a set of experimental results. a r t i c l e i n f o a b s t r a c t Article history: Large synchronization and communication overhead will become a major concern in future extreme- Received 31 July 2013 scale machines (e.g., HPC systems, supercomputers). These systems will push upwards performance limits Received in revised form by adopting chips equipped with one order of magnitude more cores than today. Alternative execution 9 October 2014 models can be explored in order to exploit the high parallelism offered by future massive many-core chips. Accepted 28 December 2014 This paper proposes the integration of standard cores with dedicated co-processing units that enable Available online 8 January 2015 the system to support a fine-grain data-flow execution