中科院_专用集成电路设计_作业4实用技术.docxVIP

PAGE \* MERGEFORMAT9 Assignment 4 1. For the cascaded inverter pair shown below, using HSPICE and TSMC 0.18 μm CMOS technology model with 1.8 V power supply and assuming Ln=200 nm, Wn=400 nm, ADn=0.2 pm2, ASn=0.2 pm2, Reqn=18 KΩ for the NMOS device and Lp=200 nm, Wp=800 nm, ADp=0.4 pm2, ASp=0.4 pm2, Reqp=45 KΩ for the PMOS device, CW=0.01 fF, please measure the parasitic capacitances: Cdg1, Cdg2, Cdb1, Cdb2, Cg3, and Cg4 by HSPICE simulation; according to the values of these capacitances, compute the propagation delays: tPLH, tPHL, and tPD respectively; measure the propagation delay tPD by HSPICE simulation, and compare the value with the one just computed from (2). (Hint: For details of how to measure the parasitic capacitances of MOSFET devices in HSPICE, please refer to the “MOSFET Capacitance Models” section of the HSPICE Reference Manual: MOSFET Models, version A-2007.09, Sept. 2007, Synopsys. ) Solution: Codes $ The cascaded inverter parasitic capacitances calculation .lib D:\Program Files (x86)\synopsys\Hspice_D-2010.03-SP1\MM018.L TT * Set 0.18um library *mn d g 0 b NCH l=0.2u w=0.4u ad=0.2e-12 pd=0.4u as=0.2e-12 ps=0.4u *mn d g 0 b NCH l=0.2u w=0.4u ad=0.2e-12 pd=1.4u as=0.2e-12 ps=1.4u *three-side vdd vdd 0 1.8 *vin n1 0 0.9 pulse 0.1 1.7 150p 50p 50p 200p 600p *vin n1 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600p * m1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4p^2 pd=0.8u as=0.4p^2 ps=0.8u m1 n2 n1 vdd vdd PCH l=0.2u w=0.8u ad=0.4e-12 pd=0.8u as=0.4e-12 ps=0.8u * m2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.2p^2 pd=0.4u as=0.2p^2 ps=0.4u m2 n2 n1 0 0 NCH l=0.2u w=0.4u ad=0.2e-12 pd=0.4u as=0.2e-12 ps=0.4u m3 n3 n2 vdd vdd PCH l=0.2u w=0.8u ad=0.4p^2 pd=0.8u as=0.4p^2 ps=0.8u m4 n3 n2 0 0 NCH l=0.2u w=0.4u ad=0.2p^2 pd=0.4u as=0.2p^2 ps=0.4u c1 n2 0 0.01f *c2 n3 0 0.01f *vd d 0 1.8 vin n1 0 1.8 ac .1 *vb b 0 0 .ac dec 1 1.59155e6 1.59155e7 * Perform a frequency sweep by 1-point per decade from 1.59 to 15.9 MHz .print CGD1=par(-lx19(m2)) CGD2=par(-lx19(m1)) CDB1=par(