第三章VHDL设计初步研讨.ppt

◆ 仿真延时 【例3-10】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS signal muxval : integer range 7 downto 0; BEGIN process(i0,i1,i2,i3,a,b) begin muxval = 0; if (a = 1) then muxval = muxval + 1; end if; if (b = 1) then muxval = muxval + 2; end if; case muxval is when 0 = q = i0; when 1 = q = i1; when 2 = q = i2; when 3 = q = i3; when others = null; end case; end process; END body_mux4; 【例3-11】 LIBRARY IEEE; USE IEEE.STD_L