Lec06.pptVIP

Jin. UESTC Digital Logic Design and ApplicationJin YanhuaLecture #6 CMOS Dynamic Electrical Behavior Other CMOS Input and Output Structures 答疑安排 答疑地点： A教2楼教师休息室 电梯/(A202)旁边 答疑时间： 周二中午 1：00-2：00 周二7、8节 周四3、4节 周五3、4节 Last Time 3.5 CMOS Steady-State Electrical Behavior Logic Levels and Noise Margins Last Time Circuit Behavior with Resistive Loads The load is specified in terms of current. Last Time Circuit Behavior with Nonideal Inputs Last Time Fanout The sum of the IIL(IIH) values of the driven inputs may not exceed IOLmax (IOHmax) of the driving output Need to do Thevenin-equivalent calculation for non-gate loads (LEDs, termination resistors, etc.) Effects of Loading Unused Inputs Never be left unconnected 3.6 CMOS Dynamic Electrical Behavior Both the speed and the power consumption of a CMOS device depend to a large extent on dynamic characteristics of the device and its load. Speed depends on two characteristics: Transition Time (转换时间) Propagation Delay (传播延迟) 3.6.1 Transition Time Depend on two factors: “On” resistance of transistor Stray capacitance (寄生电容) 3.6.1 Transition Time 3.6.2 Propagation Delay 3.6.3 Power Consumption PT : the partial short-circuiting of the CMOS output structure PL : the capacitive load on the output Static/Quiescent Power Dissipation Dynamic Power Dissipation 3.7 Other CMOS Input and Output Structures 1. Transmission Gates 2. Schmitt-Trigger Inputs Applications of Schmitt-Trigger 3. Three-State Outputs 4. Open-Drain Outputs 4. Open-Drain Outputs Driving LEDs Multi-source Buses Wired Logic of Open-Drain Outputs 3.8 CMOS Logic Families Electrical Characteristics (P.144-147 Table3-5/6/7) Symmetric output drive: output can sink or source equal amounts of current. 3.9 Low-Voltage CMOS Logic and Interfacing TTL Logic Families TTL Logic Levels and Noise Margins CMOS/TTL Interfacing Logic Families 3.8 CMOS Families HC, HCT High-speed CMOS TTL compatible VHC, VHCT (very) AHC, AHCT (advanced) FCT, FCT-T Chapter 3 S