2.4GHz的CMOSLNA设计与仿真精选.docxVIP

毕业设计2014年06月08日一种用于射频接受机的2.4GHz低噪声放大器设计摘要：人们生产、生活的需要促进了无线通信技术的蓬勃发展，对射频模块的性能要求也越来越高。近年来，深亚微米CMOS工艺的不断进步和射频集成电路对低成本、低功耗、高集成度的追求使得用CMOS工艺设计高性能的射频集成电路成为了研究热点。低噪声放大器（LNA）是射频前端电路的典型模块，它的性能直接决定了接收机的整体性能。作为接收机系统的第一级，LNA 主要是将天线接收到的微弱信号，将其放大供后级模块电路进行信号处理，同时要求引入很小的噪声，其性能的优良对接收机系统起着至关重要的作用。本文研究的是2.4GHz CMOS 低噪声放大器。首先对MOSFET模型和噪声特性进行分析，并给出了阻抗匹配下噪声性能优化的方法；其次，对低噪声放大器的各个指标参数进行了理论推导，并对现有的低噪声放大器的各种拓扑结构进行分析和比较，从中选择了源简并电感负反馈共源共栅结构进行LNA的设计。最后，本文采用TSMC 0.25um RF CMOS 工艺完成了一个2.4GHz的单端电感源极负反馈CascodeLNA 模块的设计，详细地给出了设计步骤，并用ADS进行了仿真。仿真结果为，IIP3=12.905dBm, P-1dB=-21.83dBm，NF=4.07dB，散射参数为：S11=-28.73dB, S22=-22.85dB,S21=21.79dB，功耗为7.6 mW，仿真结果表明，本文设计的LNA性能良好并符合设计要求。关键词：CMOS 低噪声放大器（LNA），噪声系数，电感源极，ADS仿真软件Design of a 2.4GHz CMOS LNA for RFRAbstract：According to the needs of people’s life,the application of wireless communication technique has been flourishing all the time.In recent years, the development of CMOS processing technology and the RFIC requirement of low cost,low power dissipation and high integration has made the research of a high-performance draw much more attention. Low Noise Amplifier (LNA) is a typical part of the RF Front End,its performance determines the whole receiver’s performance．As the first stage of the receiver,LNA must have a low noise figure (NF) and a big gain to amplify the weak signal coming from the antenna.This thesis focuses on the design of 2.4GHz CMOS LNA.First,it analyzes the characteristics and the noise model of MOSFET ,giving the method to optimize the noise performance under impedance matching conditions; Next, the detail indexes of the LNA are explained and all kinds of theLNA topology are compared to discuss their advantages and disadvantages.The input inductive source degenerated Cascode topology is our choice.At last,a 2.4GHz single end input inductive source degenerated CascodeLow Noise Amplifier( LNA) with TSMC 0.25um RF CMOS process is fulfilled and design steps has been given too,using ADS for simulation.The results of simulation are: IIP3=12.905dB