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杭州电子科技大学 学生实验报告 实验名称：EDA实验 姓名：王灵龙 班级 学号 时间：2012-11-19晚上8、9节 实验目的 熟悉Quartus II的VHDL文本设计流程全过程，学习含有层次结构的VHDL程序设计方法，从而引出例化语句机构的使用方法。 实验原理 半加器h_adder电路图 全加器f_adder电路图 4位全加器f4_adder电路图 VHDL代码： 1.h_adder程序 library ieee; use ieee.std_logic_1164.all; entity h_adder is port (a, b: in std_logic; co, so : out std_logic); end entity h_adder; architecture fh1 of h_adder is begin so = a xor b; co = a and b; end architecture fh1; 2. f_adder程序 library ieee; use ieee.std_logic_1164.all; entity f_adder is port (ain, bin, cin : in std_logic; cout, sum : out std_logic); end entity f_adder; architecture fh1 of f_adder is component h_adder port(a, b :in std_logic; co, so : out std_logic); end component; component or2a port (a, b : in std_logic; c : out std_logic); end component ; signal d, e, f : std_logic; begin u1 : h_adder port map(a=ain, b = bin, co = d, so = e); u2 : h_adder port map(a = e, b = cin, co = f, so = sum); u3 : or2a port map(a = d, b = f, c = cout); end architecture fh1; 3. f4_adder程序 library ieee; use ieee.std_logic_1164.all; entity f4_adder is port (a1, a2, a3, a4, b1, b2, b3, b4, din : in std_logic; dout, s1, s2, s3, s4 : out std_logic); end entity f4_adder; architecture fh1 of f4_adder is component f_adder port (ain, bin, cin : in std_logic; cout, sum : out std_logic); end component; signal c1, c2, c3 : std_logic; begin u1 : f_adder port map(ain = a1, bin = b1, cin = din, cout = c1, sum = s1 ); u2 : f_adder port map(ain = a2, bin = b2, cin = c1, cout = c2, sum = s2 ); u3 : f_adder port map(ain = a3, bin = b3, cin = c2, cout = c3, sum = s3 ); u4 : f_adder port map(ain = a4, bin = b4, cin = c3, cout = dout, sum = s4 ); end architecture fh1; 4. or2a程序 library ieee; use ieee.std_logic_1164.all; entity or2a is port (a, b : in std_logic; c : out std_logic); end entity or2a; architecture one of or2a is begin c = a or b; end architecture one; 仿真波形图： h_adder程序仿真图 f_adder程序仿真图 f4_adder程序仿真图