经典VHDL程序.doc

经典VHDL程序 波形发生器 Library IEEE ; use IEEE.std_logic_1164.all ; use IEEE.std_logic_arith.all ; package waveform_pkg is constant rom_width : integer := 6 ; subtype rom_word is std_logic_vector ( 1 to rom_width) ; subtype rom_range is integer range 0 to 12 ; type rom_table is array ( 0 to 12) of rom_word ; constant rom_data : rom_table := rom_table( 111010 , 101000 , 011000 , 001000 , 011010 , 010011 , 101110 , 110100 , 001010 , 001000 , 010110 , 010101 , 001111 ) ; subtype data_word is integer range 0 to 100 ; subtype data_range is integer range 0 to 12 ; type data_table is array (0 to 12) of data_word ; constant data : data_table := data_table(1,40,9,2,2,4,1,15,5,1,1,3,1) ; end waveform_pkg ; LIBRARY IEEE ; USE IEEE.std_logic_1164.ALL ; USE IEEE.std_logic_arith.ALL ; USE work.waveform_pkg.all ; entity smart_waveform is port ( clock : in std_logic ; reset : in boolean ; waves : out rom_word ) ; end ; architecture rtl of smart_waveform is signal step,next_step : rom_range ; signal delay : data_word ; begin next_step = rom_rangehigh when step = rom_rangehigh else step + 1 ; time_step : process begin wait until clockevent and clock = 1 and clocklast_value = 0; if (reset) then step = 0 ; elsif (delay = 1) then step = next_step ; else null ; end if ; end process ; delay_step : process begin wait until clockevent and clock = 1 ; if (reset) then delay = data(0) ; elsif (delay = 1) then delay = data(next_step) ; else delay = de