High Level Synthesis.pptVIP

Binding Assignment to resource instances: Operations to functional unit instances Values to be stored to instances of storage elements Data transfers to bus instances Fall 2010 Electronic Design Automation VII-* Optimization goal Minimize total cost of functional units, register, bus driver, and multiplexor Minimize total interconnection length Constraint on critical path delay Fall 2010 Electronic Design Automation VII-* Approaches to Allocation/Binding（1） Constructive --- start with an empty datapath and add functional, storage and interconnects as necessary Greedy algorithms：perform allocation for one control step at a time Rule-based：used to select type and numbers of function units, especially prior to scheduling. Fall 2010 Electronic Design Automation VII-* Approaches to Allocation/Binding（2） Graph-theoretical formulations： sub-tasks are mapped into well-defined problems in graph theory Clique partitioning Left-edge algorithm Graph coloring Fall 2010 Electronic Design Automation VII-* Example Fall 2010 Electronic Design Automation VII-* /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan 调度：确定设计执行的每个操作过程中的时间步长。 Binding：绑定，决定设计中的操作、变量和数据传输与资源配置中 特定资源的对应关系。 /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan Constant folding：常量折叠，简单来说就是将常量表达式计算求值，并用求得的值来替换表达式，放入常量表。 /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan 常量叠算/合并(Constant folding) /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan Constant and variable propagation:编译器最优化技术; Common sub-expression elimination:公共子表达式消除(CSE)，在编译器理论中的一个术语， 是寻找重复冗余表示式估算的实践，和用一单个计算赋值给一个临时变量替代它们; Operator strength reduction :操作强度折减； /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan Temporal ordering: 时空顺序 /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan In the left schedule, how many multipliers do we need? How many ALU’s? What about the schedu