第3讲_VHDL组合逻辑电路设计汇总.ppt

实体（ENTITY） 结构体（ARCHITECTURE） 直接用‘+’完成一位全加器描述 LIBRARY IEEE; --1位二进制全加器设计描述 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY adder IS PORT (ain,bin,cin : IN STD_LOGIC; cout,sum : OUT STD_LOGIC ); END ENTITY adder; ARCHITECTURE RTL OF adder IS SIGNAL ADDO : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN ADDO=( ‘0’AIN)+ BIN +CIN; SUM=ADDO(0); COUT=ADDO(1); END ARCHITECTURE RTL; LIBRARY IEEE; --8位二进制全加器顶层设计描述 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY adder IS PORT (ain,bin : IN STD_LOGIC_VECTOR(7 DOWNTO 0); cin : IN STD_LOGIC; cout : OUT STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY adder; ARCHITECTURE RTL OF adder IS SIGNAL ADDO : STD_LOGIC_VECTOR(8 DOWNTO 0); BEGIN ADDO= (‘0’AIN)+ （’0’BIN) + ( CIN); DOUT=ADDO(7 DOWNTO 0); COUT=ADDO(8); END ARCHITECTURE RTL; 3.5.9 数据类型转换函数 表 IEEE库类型转换函数表 9.3 子程序9.3.3 转换函数 【例】 LIBRARY IEEE; USE IEEE. std_logic_1164.ALL; ENTITY exg IS PORT (a,b : in bit_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end ; architecture rtl of exg is begin q= to_stdlogicvector(a and b); --将位矢量数据类型转换成标准逻辑位矢量数据 end; 【例】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;--注意使用了此程序包 ENTITY axamp IS PORT(a,b,c : IN integer range 0 to 15 ; q : OUT std_logic_vector(3 downto 0) ); END; ARCHITECTURE bhv OF axamp IS BEGIN q = conv_std_logic_vector(a,4) when conv_integer(c)=8 else conv_std_logic_vector(b,4) ; END; 【例】LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE n_pack IS SUBTYPE nat IS Integer range 0 to 255; --定义一个Integer的子类型 TYPE Bit8 IS array (7 downto 0) OF std_logic; -- 定义一个数据类型 FUNCTION nat_to_Bit8 (s: nat) R