!04synthesis高级解读.ppt

张万荣 2012 VLSI CAD VLSI CAD(2012~2013年第一学期) 北京工业大学 电子科学与技术学科部 张万荣 教授 第4章 高级综合技术（High-level synthesis） 综合技术 4.1 高级综合技术概述 4.1 高级综合流程（其一） 高级综合流程（其二） 高级综合技术 数据通道的综合 控制器综合： 结果生成与反编译： 结果生成与反编译： 结果生成与反编译： 结果生成与反编译： 控制器数据通路例子 控制器数据通路例子 4.1 高级综合技术概述---小结 4.2 高级综合结果的应用 High-level synthesis has also other uses: 4.3 行为描述、编译和转换 Functional modeling code in VHDL Data dependencies Data flow graph（数据流图） Data flow graph construction Data flow graph construction, cont’d 4.4　调度和分配 Goals of scheduling and allocation Data flow to data path-controller Binding values to registers（寄存器） Choosing function units Building the sequencer 4. 5 高级综合折衷，调度分配方法 Finding schedules ASAP and ALAP schedules Critical path of schedule Operator chaining 4.6 控制器综合 ４.6 控制器综合 Controllers and scheduling Distributed control Synchronized communication between FSMs Hardwired vs. microcoded control Controller implementation styles Data path-controller delay Architectures for low power Architecture-driven voltage scaling Power-down modes 总结与习题 Supplement Materials High Level Synthesis (HLS) The process of converting a high-level description of a design to a netlist Input: High-level languages (e.g., C) Behavioral hardware description languages (e.g., VHDL) Structural HDLs (e.g., VHDL) State diagrams / logic networks Tools: Parser Library of modules Constraints: Area constraints (e.g., # modules of a certain type) Delay constraints (e.g., set of operations should finish in l clock cycles) Output: Operation scheduling (time) and binding (resource) Control generation and detailed interconnections Scheduling and binding can be done in different orders or together Schedule: Mapping of operations to time slots (cycles) A scheduled sequencing graph is a labeled graph For each operation, define its type. For each resource, define a resource type, and a delay (in terms of # cycles) T is a relation that maps an operation to a resource type that can implement it T : V ? {1, 2, ..., nres}. More general case: A resource