基于FPGA的并串转换(状态机).docVIP

基于FPGA的并串转换（状态机） 端口说明： ale：单片机发送数据标志位 clk：输入时钟 clr：清零，低电平有效 data_p0：地址端口（由图可得，这里FPGA的地址 数据低八位 Data_p2：数据高八位（这里需要进行串化的并行数据为P2P0，图中为1011011001001101） wr：写使能，低有效 q：串行输出 s_clk：串行输出同步脉冲 ld：并串转换结束标志 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity chuanchu is port(clk:in std_logic; clr:in std_logic; ale:in std_logic; data_p0:in std_logic_vector(7 downto 0); data_p2:in std_logic_vector(7 downto 0); ld:buffer std_logic; wr:in std_logic; q:out std_logic; s_clk:buffer std_logic); end entity chuanchu; architecture art of chuanchu is signal ram_addr:std_logic_vector(7 downto 0); type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17); signal c_s,n_s:state; signal reset:std_logic; signal temp:std_logic_vector(15 downto 0); begin process(clk) begin if(ale=1and wr=1)then ram_addr=data_p0; end if; end process; process (ale,wr,ram_addr) is begin if clr=0 then reset=0; end if; if(ram_addrnd ale=0and wr=0)then temp=data_p2data_p0;reset=1; end if; end process; process(RESET,CLK)is begin if clr=0 then c_s=s0; elsif(clkevent and clk=1)then c_s=n_s; end if; end process ; com:process(c_s)is begin if clr=0 then ld=0; end if; if(reset=1 and ld=0)then n_s=s1; else n_s=s0; end if; case c_s is when s0=q=0;s_clk=0; when s1=Q=temp(15);s_clk=clk; n_s=s2; when s2=q=temp(14);s_clk=clk; n_s=s3; when s3=q=temp(13);s_clk=clk; n_s=s4; when s4=q=temp(12);s_clk=clk; n_s=s5; when s5=q=temp(11);s_clk=clk; n_s=s6; when s6=q=temp(10);s_clk=clk; n_s=s7; when s7=q=temp(9);s_clk=clk; n_s=s8; when s8=q=temp(8);s_clk=clk; n_s=s9; when s9=q=temp(7);s_clk=clk; n_s=s10; when s10=q=temp(6);s_clk=clk; n_s=s11; when s11=q=temp(5);s_clk=clk; n_s=s12; when s12=q=temp(4);s_clk=clk; n_s=s13; when s13=q=temp(3);s_clk=clk; n_s=s14; when s14=q=temp(2);s_clk=clk; n_s=s15; when s15=q=temp(1);s_clk=clk; n_s=s16; when s16=q=temp(0);s_clk=clk; n_s=s17; when s17=q=0; n_s=s0; ld=1; end case; end process; end archi