(精)超大CMOS集成电路原理chapter5.pptVIP

EE141 EE141 Digital Integrated CircuitsA Design Perspective The CMOS Inverter: A First Glance CMOS Inverter Two Inverters CMOS InverterFirst-Order DC Analysis CMOS Inverter: Transient Response Voltage TransferCharacteristic PMOS Load Lines CMOS Inverter Load Characteristics CMOS Inverter VTC Switching Threshold as a function of Transistor Ratio Determining VIH and VIL Inverter Gain Gain as a function of VDD Simulated VTC Impact of Process Variations Propagation Delay CMOS Inverter Propagation DelayApproach 1 CMOS Inverter Propagation DelayApproach 2 CMOS Inverters Transient Response Design for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase VDD (????) Delay as a function of VDD Device Sizing NMOS/PMOS ratio Impact of Rise Time on Delay Inverter Sizing Inverter Chain Inverter Delay Inverter with Load Inverter with Load Delay Formula Apply to Inverter Chain Optimal Tapering for Given N Optimum Delay and Number of Stages Example Optimum Number of Stages Optimum Effective Fanout f Impact of Self-Loading on tp Normalized delay function of F Buffer Design Power Dissipation Where Does Power Go in CMOS? Dynamic Power Dissipation Transistor Sizing for Minimum Energy Goal: Minimize Energy of whole circuit Design parameters: f and VDD tp ? tpref of circuit with f=1 and VDD =Vref Transistor Sizing (2) Performance Constraint (g=1) Energy for single Transition Transistor Sizing (3) Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 fopt(energy)=3.53, fopt(performance)=4.47 Impact ofTechnology Scaling Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a