Chapter5InterconnectRLCModel.ppt

Chapter 5 Interconnect RLC Model Efficient capacitance model Efficient inductance model RC and RLC circuit model generation Numeric based interconnect modeling Is RC Model still Sufficient? Interconnect impedance is more than resistance Z ? R +j?L ? ? 1/tr On-chip inductance should be considered When ?L becomes comparable to R as we move towards Ghz+ designs Candidates for On-Chip Inductance Wide clock trees Skews are different under RLC and RC models Neighboring signals are disturbed due to large clock di/dt noise Fast edge rate (~100ps) buses RC model under-estimates crosstalk P/G grids (and C4 bumps) di/dt noise might overweight IR drop Resistance vs Inductance Impact of Inductance Inductance Extraction from Geometries Definition of Loop Inductance The loop inductance is Loop Inductance for N Traces Assume edge traces are AC-grounded leads to 3x3 loop inductance matrix Inductance has a long range effect non-negligible coupling between t1 and t3, even with t2 between them Table in Brute-Force Way is Expensive Self inductance has nine dimensions: (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR) Mutual inductance has ten dimensions: (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR) Length is needed because inductance is not linearly scalable Definition of Partial Inductance Partial inductance is the portion of loop inductance for a segment when its current returns via the infinity called partial element equivalent circuit (PEEC) model If current is uniform (no skin effect), the partial inductance is Partial Inductance for N Traces Foundation I The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency). Foundation II The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency). Foundation III The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length,