Cacheorganization(review).pptVIP

Cache organization (review) Addressing the cache (review) Address A is in the cache if its tag matches one of the valid lines in the set associated with the set index of A Parameters of cache organization B = 2b = line size E = associativity S = 2s = number of sets Cache size = B × E × S Other parameters: s = set index b = byte offset t = tag m = address size t + s + b = m Determining cache parameters Suppose we are told we have a 8 KB, direct-map cache with 64 byte lines, and the word size is 32 bits. A direct-map cache has an associativity of 1. What are the values of t, s, and b? B = 2b = 64, so b = 6 B × E × S = C = 8192 (8 KB), and we know E = 1 S = 2s = C / B = 128, so s = 7 t = m – s – b = 32 – 6 – 7 = 19 One more example Suppose our cache is 16 KB, 4-way set associative with 32 byte lines. These are the parameters to the L1 cache of the P3 Xeon processors used by the fish machines. B = 2b = 32, so b = 5 B × E × S = C = 16384 (16 KB), and E = 4 S = 2s = C / (E × B) = 128, so s = 7 t = m – s – b = 32 – 5 – 7 = 20 * ????? B–1 1 0 ????? B–1 1 0 valid valid tag tag set 0: B = 2b bytes per cache block E lines per set S = 2s sets t tag bits per line 1 valid bit per line ????? ????? B–1 1 0 ????? B–1 1 0 valid valid tag tag set 1: ????? ????? B–1 1 0 ????? B–1 1 0 valid valid tag tag set S-1: ????? ????? Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data. t bits s bits b bits 0 m-1 tag set index Address A: ????? B–1 1 0 ????? B–1 1 0 v v tag tag set s: ????? line offset 0 31 5 12 t = 19 s = 7 b = 6 0 31 4 11 t = 20 s = 7 b = 5 * * *