IOandBus-北京大学微处理器研究开发中心.ppt

Let me show you what I mean. For example here, the CPU receives a keyboard interrupt request in the middle of the Divide instruction. If the divide instruction causes an divide by 0 exception , we have to handle it immediately. But here we have an interrupt, we can say, well, I have been spending all this time doing this divide and is almost finish, let’s wait. So the interrupt is not taken until after the divide instruction has completed. As far as generating the interrupt target address is concerned, we also have two options. First is the low cost version. We make all interrupts go to a common address and let the software to figure out what to do next. Then for those you like to built complicated hardware, you can make the hardware automatically branch to different addresses based on the interrupt type and/or level. This is called vectored interrupt. +2 = 70 min. (Y:50) Finally, lets see how we can delegate some of the I/O responsibilities from the CPU. The first option is Direct Memory Access which take advantage of the fact that I/O events often involve block transfer: you are not going to access the disk 1 byte at a time. The DMA controller is external to the processor and can acts as a bus master to transfer blocks of data to or from memory and the I/O device without CPU intervention. This is how it works. The CPU sends the starting address, the direction and length of the transfer to the DMA controller and issues a start command. The DMA controller then take over from there and provides handshake signals required (point to the last text block) to complete the entire block transfer. So the DMA controller are pretty intelligent. If you add more intelligent to the DMA controller, you will end up with a IO processor or IOP for short. +2 = 72 min. (Y:52) The IOP is so smart that the CPU only needs to issue a simple instruction (Op, Device, Address) that tells them what is the target device and where to find more commands (Addr). The IOP will then fetch comm