ppt课件-digitalsystemshardwareorganizationanddesign.pptVIP

ppt课件-digitalsystemshardwareorganizationanddesign.ppt

  1. 1、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
  2. 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  3. 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
  4. 4、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
  5. 5、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们
  6. 6、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
  7. 7、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
ppt课件-digitalsystemshardwareorganizationanddesign

Veton K?puska Digital Systems: Hardware Organization and Design Architecture of a Respresentative 32 Bit Processor Computer Architecture Chapter 3: RISC vs CISC Chapter Outline Machine Characteristics and Performance RISC versus CISC Practical Aspects of Machine Cost-Effectiveness Cost for useful work is fundamental issue Mounting, case, keyboard, etc. are dominating the cost of integrated circuits Upward compatibility preserves software investment Binary compatibility Source compatibility Emulation compatibility Performance: strong function of application Performance Measures MIPS: Millions of Instructions Per Second Same job may take more instructions on one machine than on another MFLOPS: Million Floating Point OP’s Per Second Other instructions counted as overhead for the floating point Whetstones: Synthetic benchmark A program made up to test specific performance features Dhrystones: Synthetic competitor for Whetstone Made up to “correct” Whetstone’s emphasis on floating point SPEC: Selection of “real” programs Taken from the C/Unix world CISC Versus RISC Designs CISC: Complex Instruction Set Computer Goal to minimize number of instructions Expensive Memory Many complex instructions and addressing modes More complex instructions harder to optimize their execution and increase speed. Some instructions take many steps to execute Not always easy to find best instruction for a task RISC: Reduced Instruction Set Computer Few, simple instructions, addressing modes Usually one word per instruction May take several instructions to accomplish what CISC can do in one Takes advantage of fast cashes and cheep memory Complex address calculations may take several instructions Usually has load-store, general register ISA Design Characteristics of RISCs Simple instructions can be done in few clocks Simplicity may even allow a shorter clock period A pipelined design can allow an instruction to complete in every clock period Fixed length instructions simplify fetch and decode

文档评论(0)

bgl001 + 关注
实名认证
文档贡献者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档