DDR3测试指导解读.doc

DDR3 测试指导 DDR3 的读写操作区别： 读操作时，DQS信号的边沿与DQ信号同沿（边沿对齐），用DQS的前导码触发（两个周期宽度）； 写操作时，DQS信号的边沿与DQ信号的中心对齐，用ODT下降沿触发， 读操作用DQS触发 1、DDR3 测试关于过冲的规定 （a）地址、控制信号的过冲定义： VDD=1.5V 地址控制钱最大电压值高电平Vmax= VDD + 0.4V，低电平Vmin = VDD - 0.4V 绿色区域 过冲，只要过冲面积不超，可以接受。 （b）时钟、数据信号的过冲定义： 1、 DDR3 Slew Rate 2、单端信号： 3 、差分信号如下： 4、差分信号交叉点：（CKDQS） 两个4G单端探头测试。 斜率的测量：（差分信号CK DQS） 用差分探头测量。 地址控制建立时间，保持时间的确定 数据的建立保持时间 7、地址数据建立、保持时间的量取Address / Command Setup, Hold and Derating (Cont’d) Vih(dc),Vil(dc) = VREF +- 150mv Vin(ac),Vil(ac) = VREF +- 175mv CK 与DQS 时序 tDSS 建立时间，量取DQS的下降沿Vil(ac) 到 CK 上升沿Vref 的时间； tDSH 保持时间，量取CK的上升沿Vref 到 DQS的Vih(ac)的下降沿时间； tDQSS 量取DQS上升沿的Vref到CK上升沿的Vref 时间。 DQS前导 RESET 复位信号 3.3 RESET and Initialization Procedure 3.3.1 Power-up Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined). RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300 mv to VDDmin must be no greater than 200 ms; and during the ramp, VDD VDDQ and (VDD - VDDQ) 0.3 volts. ? VDD and VDDQ are driven from a single power converter output, AND ? The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95 V max once power ramp is finished, AND ? Vref tracks VDDQ/2. OR ? Apply VDD without any slope reversal before or at the same time as VDDQ. ? Apply VDDQ without any slope reversal before or at the same time as VTT Vref. ? The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. Aft