10第4章组合与时序逻辑的设计6.docVIP

第4章 组合与时序逻辑的设计 第六节 存储结构 重点内容： Register file SRAM； single-port RAM； dual-port RAM； ROM； An embedded application may require storage elements for various purposes. No single type of memory can satisfy all criteria. There is usually a trade-off between the size and performance. Although memory modules have a similar internal structure, there are many subtle differences in their interfaces, such as the numbers of read and write ports, clocking scheme, data and address buffering, enable and reset signals, and initial values. Although it is possible to describe the desired module behaviors in HDL code, the synthesis software may or may not recognize the designers intention. Therefore, the HDL code cannot always infer the proper memory module and is normally not portable. In Altera Quartus II, there are two methods to incorporate an embedded memory module into a design: HDL instantiation via the MegaWizard Plug-in Manager program HDL inference with behavioral template The first one is specific for Altera devices and the second is a semi-device-independent behavioral description. Instantiation via MegaWizard Plug-in Manager MegaWizard Plug-in Manager is a utility program to generate Altera-specific components. It can be invoked in the Quartus II GUI by selecting ToolMegaWizard Plug-in Manager. A dialog appears and the program guides the user through a series of questions and then generates several files. The file with the .qip extension is a text file that contains the information about the core. The file with the .vhd extension contains the instantiated component and wrapping code. HDL inference with behavioral template Although it is not possible to develop a device-independent HDL description, the Quartus II manual suggests a collection of behavioral HDL templates to infer memory modules for Altera FPGA devices. These templates are done by behavioral descriptions and contain no device-specific component instantiation. They are easy to understand and can be simu