VHDL设计乒乓球机.docVIP

entity displayled is --秒表 Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; boma : in std_logic_vector(1 downto 0); ledA : out STD_LOGIC_VECTOR (7 downto 0); ledK : out STD_LOGIC_VECTOR (5 downto 0)); end displayled; architecture Behavioral of displayled is signal counter1ms:std_logic_vector(15 downto 0); signal counter1s:std_logic_vector(25 downto 0); signal num6:integer range 0 to 5; --shu ma guan xuan tong signal displaynum:std_logic_vector(3 downto 0); signal count24:std_logic_vector(23 downto 0); begin process(rst,clk) begin if rst=0 then counter1ms=(others=0); num6=0; elsif rising_edge(clk) then if counter1ms(15)=1 then counter1ms=(others=0); if num6=5 then num6=0 ; else num6=num6+1; end if; else counter1ms=counter1ms+1; end if; end if; end process process(rst,clk) begin if rst=0 then displaynum=0000; ledK=000000; elsif rising_edge(clk) then case num6 is when 0 =ledK=000001; displaynum=count24(3 downto 0); when 1 =ledK=000010; displaynum=count24(7 downto 4); when 2 =ledK=000100; displaynum=count24(11 downto 8); when 3 =ledK=001000; displaynum=count24(15 downto 12); when 4 =ledK=010000; displaynum=count24(19 downto 16); when 5 =ledK=100000; displaynum=count24(23 downto 20); when others =ledK=000000; displaynum=0000; end case; end if; end process process(rst,clk) variable Fre: integer range 610 to-- : begin if rst=0 then counter1s=(others=0); count24=(others=0); elsif rising_edge(clk) then --with boma select --Fre:=610 when 00, --156160 when 01, -when 10, -when others; --Fre:=610 when boma=00 else --1561160 when boma=01 else -when boma=10 else -; case boma is --change frequency when 00=Fre:=610; when 01=Fre:=15160; when 1