数字电子技术基础赵莹CH5CH58课件教学.pptVIP

* 触发器 在线教务辅导网： 更多课程配套课件资源请访问在线教务辅导网 5.8四种基本触发器的VHDL描述 1. RS触发器 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity rsff is port(r,s,clk:int std_logic; q,qb:buffer std_logic)； end rsff; architecture rsff_art of rsff is signal q_s,qb_s; std_logic; begin process（clk,r,s） begin if (clk’event and clk=’1’)then if (s=’1’and r=’0’)then q_s=’0’; qb_s=’1’; elseif (s=’0’and r=’1’)then q_s=’1’; qb_s=’0’; elseif (s=’0’and r=’0’)then q_s=q_s; qb_s=qb_s; end if; end if; q_s=q_s; qb_s=qb_s; end process; end rsff_art; 2.同步复位的D触发器 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity syndff is port(d,clk,reset:in std_logic; q,qb:out std_logic)； end syndff; architecture dff_art of syndff is begin process（clk） begin if (clk’event and clk=’1’)then if (reset=’0’)then q =’0’; qb=’1’; else q =d; qb=not q; end if; end if; end process; end dff_art; 3.异步复位/置位的JK触发器 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity asynjkff is port(j,k,clk,set.reset:int std_logic; q,qb:out std_logic)； end asynjkff; architecture jkff_art of asynjkff is signal q_s,qb_s; std_logic; begin process（clk,set,reset） begin if (set=’0’and reset=’1’)then if (s=’1’and r=’0’)then q_s=’1’; qb_s=’0’; elseif if (set=’1’and reset=’0’)then q_s=’0’; qb_s=’1’; elseif(clk’event and clk=’1’)then if (j=’0’and k=’1’)then q_s=’0’; qb_s=’1’; elseif (j=’1’and k=’0’)then q_s=’1’; qb_s=’0’; elseif (j=’1’and k=’1’)then q_s=not q_s;