Optimality Study of Logic Synthesis for LUTBased FPGAs最优性为基于LUT的FPGA逻辑综合的研究.pptVIP

* * * * * * Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs  Kirill Minkovich and Jason Cong VLSI CAD Lab Computer Science Department University of California, Los Angeles Supported by the National Science Foundation under grant CCF-0530261 Variation and its effects Environmental Variation Causes: overheating and voltage fluctuations Addressed (in part) by: cooling and better power supplies Process Variation Causes: dopant density, edge geometry, stress during manufacturing, and much more Addressed (in part) by: Adding a slack of as much as 3-sigma for delay variation Data Variation Causes: output stabilization varying greatly between different data Addressed by: Highly restrictive asynchronous designs and the Razor architecture Solutions Speed Binning and more accurate estimates Only deals with process variation Variable Clocking (Razor Architecture) Deals with all 3 variations! Intra-die variations in ILD thickness High performance circuits Worst-case delay minimization Hitting a wall due to feature size limits Can’t keep up with Moore’s law Conservative timing due to variation Typical case delay minimization Defined: Delay for expected data to propagate through circuit Usually much smaller than worst-case delay Harder to optimize circuits Change thinking about circuit optimization Requires special architecture, like the Razor Architecture (MICRO ’03) UCLA VLSICAD LAB * Razor flip-flop implementation Error comparator RAZOR FF Main Flip-Flop clk clk_del Shadow Latch Q Logic Stage L1 Logic Stage L2 Error_L 0 1 D Slide borrow from Razor (MICRO ’03) presentation Main flip-flop Clocked faster than worst-case delay Shadow Latch Clocked with delayed clock to catches any errors Error Occurs when main flip-flop and shadow latch differ Next clock cycle, the Shadow latch value moves into the Main Flip-Flop * Razor timing error detection Second sample of logic value used to validate earlier sample Key design iss