The Art of Multiprocessor Programming Elsevier Store多处理器编程的艺术爱思店.pptVIP

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The Art of Multiprocessor Programming Elsevier Store多处理器编程的艺术爱思店.ppt

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The Art of Multiprocessor Programming Elsevier Store多处理器编程的艺术爱思店

? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * Many processors have write buffers. When a processor issues a write, it isn’t necessarily sent to memory right away. Instead it may be queued up in a write (or store) buffer. If the processor writes twice to the same location, the earlier write can be absorbed, that is, overwritten without ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * Wait … ? 2003 Herlihy and Shavit * And then get an acknowledgement that the new value was actually installed in the memory. ? 2003 Herlihy and Shavit * We alleviate this problem by introducing one or more caches: small, fast memories situated between main memory and processors. ? 2003 Herlihy and Shavit * Now, when a processor reads a value from memory, it stores the data in the cache before returning the data to the processor. ? 2003 Herlihy and Shavit * Later, if the processor wants to use the same data … ? 2003 Herlihy and Shavit * When a processor wants to read a value, it first checks whether the data is present in the cache … ? 2003 Herlihy and Shavit * If so, it reads directly from the cache, saving a long round-trip to main memory. We call this a cache hit. ? 2003 Herlihy and Shavit * Sometimes the processor doesn’t find what it is lookin for in the cache. ? 2003 Herlihy and Shavit * We call this a cache miss. ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * We will discuss the ideas in this slide when talking about spin-locks ? 2003 Herlihy and Shavit * caches typically operate at a granularity larger than a single word: a cache holds a group of neighboring words called a cache line. (sometimes called a cache block). ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * ? 2003 Herlihy and Shavit * In practice, most processors have two levels of caches, called