Using Compression to Improve Chip Multiprocessor Performance利用压缩技术提高芯片多处理器性能.pptVIP

Using Compression to Improve Chip Multiprocessor Performance Alaa R. Alameldeen Dissertation Defense Wisconsin Multifacet Project University of Wisconsin-Madison /multifacet Motivation Architectural trends Multi-threaded workloads Memory wall Pin bandwidth bottleneck CMP design trade-offs Number of Cores Cache Size Pin Bandwidth Are these trade-offs zero-sum? No, compression helps cache size and pin bandwidth However, hardware compression raises a few questions Thesis Contributions Question: Is compression’s overhead too high for caches? Contribution #1: Simple compressed cache design Compression Scheme: Frequent Pattern Compression Cache Design: Decoupled Variable-Segment Cache Question: Can cache compression hurt performance? Reduces miss rate Increases hit latency Contribution #2: Adaptive compression Adapt to program behavior Cache compression only when it helps Thesis Contributions (Cont.) Question: Does compression help CMP performance? Contribution #3: Evaluate CMP cache and link compression Cache compression improves CMP throughput Link compression reduces pin bandwidth demand Question: How does compression and prefetching interact? Contribution #4: Compression interacts positively with prefetching Speedup (Compr, Pref) Speedup (Compr) x Speedup (Pref) Question: How do we balance CMP cores and caches? Contribution #5: Model CMP cache and link compression Compression improves optimal CMP configuration Outline Background Technology and Software Trends Compression Addresses CMP Design Challenges Compressed Cache Design Adaptive Compression CMP Cache and Link Compression Interactions with Hardware Prefetching Balanced CMP Design Conclusions Technology and Software Trends Technology trends: Memory Wall: Increasing gap between processor and memory speeds Pin Bottleneck: Bandwidth demand Bandwidth Supply Pin Bottleneck: ITRS 04 Roadmap Technology and Software Trends Technology trends: Memory Wall: Increasing gap between processor and memory s