高瞻计画-IC制程简介.ppt

高瞻計畫 - IC製程簡介 大安高工 電子科 張 洧 2008.4.8 資料提供 臺灣科技大學 電子工程系 陳伯奇教授 CMOS 製程介紹 CMOS 製程介紹 IC built on silicon substrate : some structures diffused into substrate. other structures built on top of substrate. Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Insulator - Silicon Dioxide (SiO2) Used to insulate transistor gates (thin oxide) Used to insulate layers of wires (field oxide) Can be grown on Silicon or Chemically Deposited CMOS 製程介紹 A View of the Cleanroom CMOS 製程介紹 (Wafer晶圓) CMOS 製程介紹 (Photolithography光罩) Coat wafer with photoresist (PR) Shine UV light through mask to selectively expose PR Now use exposed areas for Selective doping Selective removal of material under exposed PR CMOS 製程介紹 (0.25 micron transistor) CMOS 製程介紹 CMOS 製程介紹 (Example : NOT Gate) NOT Gate – Step 1 NOT Gate – Step 1 NOT Gate – Step 1 NOT Gate – Step 2 NOT Gate – Step 2 NOT Gate – Step 2 NOT Gate – Step 2 NOT Gate – Step 3 NOT Gate – Step 3 NOT Gate – Step 3 NOT Gate – Step 4 NOT Gate – Step 4 NOT Gate – Step 4 NOT Gate – Step 5 NOT Gate – Step 5 NOT Gate – Step 5 NOT Gate – Step 6 NOT Gate – Step 6 NOT Gate – Step 6 NOT Gate – Step 6 NOT Gate – Step 7 NOT Gate – Step 7 NOT Gate – Step 7 NOT Gate – Step 8 NOT Gate – Step 8 NOT Gate – Step 8 NOT Gate – Step 8 NOT Gate – Step 9 NOT Gate – Step 9 NOT Gate – Step 9 NOT Gate – Step 10+ p+ p+ p+ n n+ n+ n+ metal over poly outside of cross section Form Metal 1 Traces Pattern photoresist METAL 1 Mask (使用METAL 1光罩 曝光產生連接線路) Etch metal(移除第一金屬層) p+ p+ p+ n n+ n+ n+ Form Metal 1 Traces Pattern photoresist METAL 1 Mask (使用METAL 1光罩 曝光產生連接線路) Etch metal(移除第一金屬層) Remove photoresist(移除光阻) p+ p+ p+ n n+ n+ n+ VIA mask VIA mask Form Vias to Metal 1 Deposit oxide (沈積氧化層) Planerize oxide (磨平氧化層) Deposit photoresist(沈積光阻) p+ p+ p+ n n+ n+ n+ VIA mask VIA mask Form Vias t