STMICROELECTRONICS_SG3525AP.pdf

SG2525A SG3525A REGULATING PULSE WIDTH MODULATORS .8 TO 35 V OPERATION . 5.1 V REFERENCE TRIMMED TO ± 1 % . 100 Hz TO 500 KHz OSCILLATOR RANGE .SEPARATE OSCILLATORSYNC TERMINAL .ADJUSTABLE DEADTIME CONTROL . INTERNAL SOFT-START .PULSE-BY-PULSESHUTDOWN . INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS . LATCHING PWM TO PREVENT MULTIPLE PULSES .DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The SG3525Aseries of pulse width modulator inte- grated circuits are designed to offer improved per- formance and lowered external parts count when used in designing all types of switching power sup- plies. The on-chip + 5.1 V reference is trimmed to ± 1 % andthe inputcommon-mode rangeof the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator al- lows multiple units to beslaved or a single unit to be synchronized to an external system clock. A single resistorbetweentheCT andthe dischargeterminals provide a wide range of dead time ad- justment. Thesedevicesalso featurebuilt-insoft-startcircuitry with only an external timing capacitor required. A shutdownterminal controlsboth the soft-start circu- ity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shut- down, as well as soft-start recycle with longer shut- down commands. These functionsare also control- ledby an undervoltagelockoutwhich keepsthe out- puts off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry in- cludesapproximately500 mV of hysteresisfor jitter- free operation. Another feature of these PWM cir- cuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputswill remain off for the durationof the pe- riod. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525AoutputstagefeaturesNOR logic, givinga LOW output for an OFF state. DIP16 16(Narrow) Type Pla