Combinational Optimization Verification Challenge Necessity of Integrated Solution.pdf

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Combinational Optimization Verification Challenge Necessity of Integrated Solution.pdf

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Combinational Optimization Verification Challenge Necessity of Integrated Solution

1Logic Synthesis Verification Jie-Hong R. Jiang National Taiwan University Fall 2007 Lecture 10 2 Sequential synthesis Most of the materials are taken from A. Kuehlmann’s lecture notes 3 Overview of circuit optimization Combinational Optimization Clock Skew Scheduling Retiming Architectural Restructuring System-Level Optimization O p t i m i z a t i o n S p a c e D i s t a n c e f r o m P h y s i c a l I m p l e m e n t a t i o n V e r i f i c a t i o n C h a l l e n g e N e c e s s i t y o f I n t e g r a t e d S o l u t i o n 4 Sequential optimization techniques ? Clock skew scheduling ? balancing of path delays by adjusting the relative clocking schedule of individual registers ? Retiming ? balancing path delays by moving registers within circuit topology ? interleaving with combinational optimization techniques ? Architectural restructuring ? adding sequential redundancy ? fixed: does not change input/output behavior ? flexible: change input output behavior ? System-level optimization 5Integration in design flow ? Optimization space ? significantly more optimization freedom at a higher level for improving performance, power, area, etc. ? Distance from physical implementation ? difficult to accurately model impacts on final implementation ? difficult to mathematically characterize optimization space ? Verification challenge ? departure from combinational comparison model would impede formal equivalence checking ? different simulation behaviors cause acceptance problems Necessity of tight tool integration 6 Clock skew scheduling 4 2 5 3r1 r2 r3 r4 Dmax=0 Dmax=14 Dmin=5Dmin=0 Dmax=0 Dmin=0 Skew =0 Tcycle=14 r1, r2, r3 r4 D’max=5 D’max=9 D’min=0D’min=5 Dmax=0 Dmin=0 Skew =5 Tcycle=9 r1, r2, r3 r4 Tcycle + skew ≥ Dmax skew ≤ Dmin 0 ≤ |skew| Tcycle 0–5 7 Clock skew scheduling ? By controlling clock delays on registers, clock frequency may be increased ? Do not change transition and output functions (not the case in retiming) ? Good for functio